Various embodiments of this disclosure relate to symmetric multiprocessing (SMP) computer systems and, more particularly, to early shared resource release in SMP computer systems.
An SMP computer system may include multiple computing nodes. Within each computing node, multiple processors may be connected to a main memory for the computing node. Each processor may have its own local cache, such as an L1 cache, but the processors within a computing node may also share a cache, such as an L2 cache. Some SMP computer systems have cache coherence across all computing nodes, such that the caches of the various computing nodes maintain consistent data. To achieve this type of cache coherence, the SMP computer system operates a protocol to ensure that the data remains consistent. A benefit of cache coherence is that a main memory access may be avoidable by a computing node when that computing node experiences a cache miss when seeking a cache line in the L2 cache. In that case, the computing node may request the cache line from the other computing nodes, which may retrieve it from their own caches without a main memory access.
More specifically, when a first computing node experiences a cache miss, it broadcasts to the other computing nodes a request for the desired cache line. In response to that request, the other computing nodes expend resources handling the request. For example, each other computing node may check one or more of its own caches to determine the current state of the cache line in question. The other computing nodes then broadcast the current state of the cache line, and in response to receiving the states of the cache line at other computing nodes, each computing node updates its cache line as needed.